DR=0, MPB=0, ORER=0, FER=0, RDF=0, PER=0
Receive FIFO Data Register HL
| RDAT | Serial receive data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) |
| MPB | Multi-processor bit flag (Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) 0 (0): Data transmission cycles 1 (1): ID transmission cycles |
| DR | Receive data ready flag (It is same as SSR.DR) 0 (0): Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. 1 (1): Next receive data has not been received for a period after normal completed receiving. |
| PER | Parity error flag 0 (0): No parity error occurred at the first data of FRDRH and FRDRL. 1 (1): A parity error has occurred at the first data of FRDRH and FRDRL. |
| FER | Framing error flag 0 (0): No framing error occurred at the first data of FRDRH and FRDRL. 1 (1): A framing error has occurred at the first data of FRDRH and FRDRL. |
| ORER | Overrun error flag (It is same as SSR.ORER) 0 (0): No overrun error occurred. 1 (1): An overrun error has occurred. |
| RDF | Receive FIFO data full flag (It is same as SSR.RDF) 0 (0): The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. 1 (1): The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. |
| Reserved | This bit is read as 0. |